Superconducting Qubit Designer

The designer models the non linear quantum Hamiltonian of the transmon qubit, balancing the Josephson junction tunneling energy against the island charging energy to operate within the phase insensitive transmon regime. Conforming to standards established by the IEEE Quantum Initiative and the American Physical Society APS, the specialist utilizes finite element 3D high frequency electromagnetic simulators to compute capacitive coupling matrices, resonator quality factors, Purcell radiative decay rates, and microwave transmission line impedances. They design asymmetric SQUID loops to enable fast magnetic flux tunability while shielding against 1 over f magnetic flux noise.

While automated electronic design automation EDA scripts synthesize interdigital capacitor geometries and coplanar waveguide meander lines, microwave quantum hardware is deeply susceptible to subtle physical layout artifacts. Parasitic slotline modes, dielectric two level system TLS losses in substrate oxides, and package box resonance modes can degrade qubit relaxation times from hundreds of microseconds down to nanoseconds. The transmon circuit designer analyzes qubit layout geometries with microwave engineering rigor, collaborating directly with nanofabrication cleanrooms and low temperature experimentalists to translate theoretical quantum gates into physical silicon and sapphire hardware.

The day starts at eight in the morning at the quantum architecture workstation. The designer is finalizing the layout of a sixteen qubit superconducting processor test tile fabricated on high resistivity silicon. Opening Ansys HFSS, they inspect the 3D finite element mesh around a newly designed concentric transmon qubit, reviewing the computed electric field energy participation ratios across the metal substrate interface to verify that dielectric loss tangents will support an expected T1 relaxation time exceeding one hundred and fifty microseconds. The designer shifts focus to the microwave readout circuitry. To enable fast, multiplexed single shot dispersive readout across four

qubits per feedline, they design quarter wave coplanar waveguide resonators with staggered fundamental frequencies between 6.5 and 7.2 gigahertz. They insert an on chip Purcell filter consisting of a stepped impedance bandpass filter between the readout resonators and the common launch pad. Simulating the S21 transmission response, they confirm that the filter suppresses spontaneous qubit decay through the feedline by two orders of magnitude while allowing rapid readout probe pulses to pass unattenuated. In the afternoon, the designer joins a design review with the cleanroom lithography team. They examine scanning.

A Superconducting Qubit Transmon Circuit Designer designs, models, simulates, and optimizes planar microwave integrated circuits featuring superconducting transmons, fluxonium qubits, readout resonators, and Purcell filter networks that form the core processing fabric of superconducting quantum computers. Operating across quantum hardware corporations, national research laboratories, and semiconductor design centers, the designer crafts quantum circuit layouts operating at gigahertz frequencies that maximize qubit coherence times while minimizing unwanted electromagnetic crosstalk and stray coupling.

Core responsibilities include design planar superconducting transmon and fluxonium qubit circuits, readout resonators, and purcell filters in layout cad., operational coordination, and ensuring strict adherence to Kenyan statutory frameworks and quality standards.

Key organizations hiring for this role include Konza Technopolis Development Authority, Safaricom Advanced Technologies Division, Kenya Bureau of Standards KEBS Metrology Division, Kenya Electricity Generating Company KenGen, alongside expanding opportunities in Nairobi, Mombasa, Kisumu, and regional infrastructure projects.

Superconducting Qubit Designer Specialist, Senior Superconducting Qubit Designer, Superconducting Qubit Designer Lead, Superconducting Qubit Designer Consultant

While automated electronic design automation EDA scripts synthesize interdigital capacitor geometries and coplanar waveguide meander lines, microwave quantum hardware is deeply susceptible to subtle physical layout artifacts. Parasitic slotline modes, dielectric two level system TLS losses in substrate oxides, and package box resonance modes can degrade qubit relaxation times from hundreds of microseconds down to nanoseconds. The transmon circuit designer analyzes qubit layout geometries with microwave engineering rigor, collaborating directly with nanofabrication cleanrooms and low temperature experimentalists to translate theoretical quantum gates into physical silicon and sapphire hardware. Employment opportunities concentrate across major industrial, commercial, and financial hubs including Nairobi, Mombasa, Kisumu, Nakuru, and Eldoret, alongside specialized regional project sites.